1. Field of the Invention
This invention relates to a semiconductor device that operates excellently in a high frequency range typically between 300 MHz and 1 GHz.
2. Description of the Related Art
A semiconductor device comprising an IC on a large scale is normally contained in a package made of ceramic or a similar material. Known techniques for preparing ceramic packages include sintering and stacking, with which packages are molded under pressure. With a stacking method, several pasty metal layers are formed on a green sheet by screen printing to produce inner leads and then sintered at high temperature around 1,500.degree. C.
A conventional semiconductor device in a ceramic package prepared by stacking will be described in greater detail by referring to FIGS. 13 through 17 of the accompanying drawings. Of these, FIG. 13 is a schematic perspective view of a conventional semiconductor device and FIG. 14 is a schematic plan view of an area surrounded by a circle A in FIG. 13. FIG. 15 is a schematic perspective view of part of the device, illustrating some of the inner leads and the semiconductor substrate of the device in an enlarged scale. The semiconductor substrate 1 which is typically made of silicon and carries an integrated circuit thereon is placed at the center of a mounting portion 2 of a ceramic substrate of, for example, aluminum nitride. The mounting portion 2 has substantially a square configuration and supports a semiconductor substrate at the center portion. Ceramic layers are formed on the periphery of the mounting portion 2. Inner leads 3 and 4 are formed on the ceramic layers to surround the semiconductor substrate 1. The inner leads are realized in a two-layer structure having a lower layer for the inner leads 3 operating as power supply leads and an upper layer for the inner leads 4 operating as signal transmission leads. End portions of the inner leads 4 which are connected to external terminals are covered by a ceramic layer that supports the inner leads 3 of the mounting portion 2.
The other ends of the inner leads 4 are exposed and opposite to the semiconductor substrate 1. End portions of the inner leads 3 which are connected to external terminals are covered by a ceramic layer that supports external terminals of the mounting portion 2. The other end of the inner leads 3 is exposed and opposite to the semiconductor substrate 1. The center portion of the mounting portion 2 constitutes a cavity 8 having a bottom 5, on which a power supply layer is arranged. The semiconductor substrate 1 carrying thereon an integrated circuit is fixed to the mounting portion 2 by using an electrically conductive adhesive agent 6 such as epoxy resin. The inner leads 3 and 4 are connected to electrodes (not shown) such as signal transmission pads and power supply pads. The power supply leads of the inner leads 3 are connected to the power supply layer at the cavity bottom 5. The external terminals 9 are pin-shaped and provided on the surface region of a peripheral region of mounting portion 2 and electrically connected to the inner leads 3 and 4 by way of conductive layers formed within the mounting portion 2. The semiconductor substrate 1, bonding wires and other components are sealed by means of a cap (not shown).
A conventional semiconductor device having a configuration as described above comprises a mounting portion for carrying thereon a semiconductor substrate on which two or more layers of inner leads are superposed to produce a multilayer structure. The inner lead layer for signal transmission is provided separately from the inner lead layer for power supply, so that the device has a good high frequency characteristic. The semiconductor substrate is mounted on a cavity formed in the center portion of the mounting portion. The cavity has a substantially square profile that matches the profile of the semiconductor substrate. The mounting portion also has a substantially square profile. Thus, bonding wires of the device have different lengths that vary depending on their relative locations on the semiconductor substrate. Those of the bonding wires located at the corners of the semiconductor substrate are much longer than those located at the middle of the edges. The differences in the length of the bonding wires are reflected in differences in the electric resistance of the wires, and these differences in the electric resistance can significantly affect the performance of the device particularly at high frequencies. This wire length dependency of the electric properties of the external terminals (pins) of a semiconductor device can by turn seriously affect the performance of the integrated circuit formed on the semiconductor substrate particularly in view of the fact that more and more semiconductor devices are designed to operate at high frequencies.
Depending on the type of the semiconductor substrate fitted in the cavity, the latter may be made to have a selected electric potential in order to make the device adapted for a large electric current and/or high speed operation. However, as more and more large wafers and chips (semiconductor substrates) are used for semiconductor devices these days, they inevitably tend to become thicker and show a height greater than 290 .mu.m, which is currently prevalent and with which the inner leads can be bonded to the cavity section of the mounting portion without difficulty (FIG. 15). However, if a large semiconductor substrate show a height greater than 350 .mu.m, the tool being used for the bonding operation can hit some of the corners of the semiconductor substrate (chip) to obstruct the operation.
This problem will be described in greater detail by referring to FIGS. 16 and 17 illustrating cross sectional views of part of a mounting portion carrying thereon a semiconductor substrate (chip) and other components of a semiconductor device. In FIG. 16, there are shown a chip bonded to the mounting portion 2 by means of an electrically conductive adhesive agent 6, a bonding wire 7 and a bonding tool BT. In FIG. 17, the chip 1 is secured to the mounting portion 2. As described above, a metal layer is formed on the cavity bottom 5 of the mounting portion 2 as a power supply layer. The arrows in FIG. 16 indicate the directions along which the bonding tool BT is moved. Assume here that the inner lead (power supply lead) 3 opposing the semiconductor substrate 1 is connected to the power supply layer on the cavity bottom 5 by a bonding wire 7.
Then, the bonding tool BT is moved from the inner lead 3 toward the cavity bottom 5 and, as it comes down, it can accidentally hit a corner (surrounded by a circle) of the chip 1 to cut the bonding wire 7. Therefore, in order to prevent such an accident from occurring, the chip 1 and the inner lead 3 have to be separated from each other by a sufficiently large distance. The probability with which the bonding tool BT hits a corner of the chip 1 in a bonding operation rises with the increase in the height of the chip 1. As seen from FIG. 17, if the chip 1 and the layer of the electrically conductive bonding agent 6 stand 350 .mu.m and 60 .mu.m respectively, the smallest length "x" of a bonding wire to be bonded to the cavity bottom 5 of a chip 1 by a bonding tool BT without touching the chip 1 will be x=(350+60)/tan30.degree.=0.71 or about 0.8 mm including a safety margin, where 30.degree. is the angle defined by the length "x" and the combined height of the chip and the layer of the electrically conductive bonding agent.
When chips having respective thicknesses of 290 .mu.m, 350 .mu.m and 450 .mu.m are assessed for the probability with which the bonding tool BT accidentally hits a corner of the chip, the above defined angle may have any value between 0.degree. and 45.degree. for the bonding tool BT not to hit the corner if the chip is 290 .mu.m high, whereas the angle have to be equal to or greater than 20.degree. and 40.degree. if the height of the chip is 350 .mu.m and 450 .mu.m respectively.
Thus, it can be concluded that with a semiconductor substrate that stands 350 .mu.m or 450 .mu.m, the operation of a bonding wire can be conducted only at corners where the wire to be bonded stretches over a relatively long distance. In other words, it is difficult to bond a wire to the cavity of a mounting portion if a large thickness chip is used, resulting in reduction of the electric performance of the finished semiconductor.